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ECE Seminar

Mon, Nov. 17, 2008; 3-4pm; "Reliability of Nanoscale CMOS Devices with High-k Gate Dielectrics"

What
When Nov 17, 2008
from 03:00 pm to 04:00 pm
Where Lutz Hall Room 306
Contact Name
Contact Phone 852-6348
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The Institute for Advanced Materials and Renewable Energy (IAM-RE) and the Electrical and Computer Engineering Department are hosting a special seminar next Monday:

Reliability of Nanoscale CMOS Devices with High-k Gate Dielectrics

Durga Misra
Electrical and Computer Engineering Department
New Jersey Institute of Technology

Monday, November 17, 2008
3-4 p.m.
306 Lutz Hall

Abstract:

Stringent power requirements in the chips by the International Technology Roadmap for Semiconductors (ITRS) dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Therefore, for high speed and low power applications high-k dielectric materials are being integrated into standard CMOS technologies. At present, reliability requirements of advanced gate stacks with high-k dielectrics are of intensive research interests as these high-k dielectrics needs to meet the silicon dioxide standards. In this talk some of the on-going research work on charge trapping in high-k dielectrics such as HfO2 and HfSixOy will be discussed in detail. Detection mechanism of electrically active intrinsic traps will be outlined. Based on the negative bias temperature instability (NBTI) the results will be correlated with theoretical models. Breakdown measurements of HfO2 and HfSixO will be discussed with respect to poly and metal gates. High-k on alternate substrates like Ge substrate will also be discussed.

About the Speaker

Dr. Durga Misra is a Professor in the Department of Electrical and Computer Engineering of New Jersey Institute of Technology (NJIT). He received his M.S. and Ph.D. degrees both in Electrical Engineering from University of Waterloo, Waterloo, Canada in 1985 and 1988 respectively. He has been a faculty member since the fall of 1988 at NJIT. His current research focus is study of nanoscale CMOS gate stacks. He received several research awards from the National Science Foundation. In 1997 he worked at the VLSI Research Department at Bell Laboratories. He received IEEE Regional Activities Board’s International Leadership Award and is currently a Distinguished Lecturer of Electron Device Society of IEEE. He has organized many International Symposiums on Solid-State Science and Technology field during the Technical Meetings of the Electrochemical Society and IEEE. Currently he serves as the EDS-SRC Chair for Regions 1-3 & 7 of IEEE. He is a Fellow of the Electrochemical Society (ECS) and is currently the Chair of Dielectric Science and Technology Division of ECS. He has co-edited the High-k gate stack ECS Transaction Series.

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